In existing Liquid Crystal Display (LCD) pixel structures, particularly for pixel structures in In-Plane Switching (IPS) and Fringe Field Switching (FFS) modes, a planarization (PLN) layer will be formed before pixel electrodes are formed in order to make an electric field horizontally uniform. Furthermore, uniformly distributed vias 101 are formed in the PLN layer (as illustrated in a first scenario in FIG. 1), where the vias 101 are positioned above Thin Film Transistors (TFTs) to connect pixel electrodes of pixel elements, where the vias are positioned, with the drains of the TFTs. Particularly Photoresist Spacer (PS) 102 are positioned at locations between any two specified adjacent vias above the PLN layer to support an upper substrate, so that the cell thickness between the upper substrate and a lower substrate is maintained uniform to thereby ensure surface pressure capabilities.
In order to improve the density of display pixels of the LCD while decreasing the size of respective sub-pixels, the original size of the PLN vias has to be maintained due to a process restriction, in this way resulting in a shorter distance between the adjacent PLN vias, so that there may be an arc occurring at the support locations where the photoresist spacers are positioned, and the photoresist spacers can not come into full contact with the lower substrate; and the photoresist spacers tend to slip into the PLN vias in the case of poor bonding in a vacuum, in this way lowering the cell thickness at the locations where the photoresist spacers are positioned; and moreover the slipping photoresist spacer tend to scratch an alignment film in a manual operation process.